*Helps networks to keep pace with exploding number of internet users — from people to machines*
ARMONK, N.Y., – 09 Nov 2010: IBM today announced a new chip-making technology that can be used to create advanced semiconductors that can keep pace with the exploding number of internet-connected devices and the tidal wave of data they are generating.
The Cu-32 Custom Logic offering employs unique IBM technology — designed by IBM Research — to dramatically increase the memory capacity and processing speeds of chips used in fiber-optic and wireless networks, and in such gear as routers and switches. The technology can help manufacturers and network operators handle the data deluge driven by consumers’ appetites for smart phones and other Web-connected devices.
Systems using chips made with Cu-32 for example, can result in:
- Cellular infrastructure that can move one year’s worth of text messages (six trillion, worldwide in 2010) in less than ten seconds;(1)
- A consumer downloading a feature-length film on a smart phone in less than ten seconds; or a HD version in under a minute;(2)
- Routers that can stream every motion picture ever produced in less than one minute;(3)
The number of people using the internet has doubled in the past five years, with two billion logging-on in 2010.(4) Smart phones, game consoles, digital TVs, GPS devices and MP3 players are among the consumer gadgets that now ride the internet. As the world’s infrastructure gets further digitized, connected and monitored, vast arrays of machine-to-machine sensors are also beginning to use the internet to transmit data on commuter traffic, buildings’ energy usage or the health of newborn infants, for example. Manufacturers of communications infrastructure will increasingly need breakthrough semiconductor technologies such as Cu-32 to keep up with the demand to secure, store and move an ever-growing amount of web traffic.
Embedded Memory, Made in IBM Labs, Key to Breakthrough Performance
IBM’s embedded DRAM technology provides the most dense on-chip dynamic memory available today, enabling more than 1Gb of memory on a single chip. IBM eDRAM performance has advanced to a point where it can replace conventional on-chip static memory (SRAM) in many applications, taking up 60% less space on the chip, and consuming up to 90% less power.
“IBM’s Cu-32 technology with ARM advanced physical IP enables chip-makers to get powerful system-on-a-chip solutions quickly to market,” said Simon Segars, executive vice president and general manager, ARM physical IP division. “Our collaboration with IBM allows both companies to advance the state-of-the-art in the low-power embedded semiconductors that will help create next-generation networks.”
A suite of new high-sped serial cores (HSS) give Cu-32 advanced capabilities to network with more than a dozen different interface standards. Additionally, IBM’s silicon-on-insulator (SOI) process helps improve energy efficiency in chips using Cu-32. Since its invention by IBM in 1998, more than 100 million SOI chips have been shipped, powering the newest generation of video games and enabling a wide range of enhanced communications applications. More than twenty of the world’s leading semiconductor makers, tool makers and industry suppliers are members of the SOI Industry Consortium, setting the course of future SOI innovation.
“By any measure – from the growing number of mobile users to the explosion we’re seeing in data — network traffic will grow at a pace we haven’t seen before,” said Mark Ireland, VP, Semiconductor Products, IBM. “Cu-32, our most advanced Custom Logic offering, with the industry’s best eDRAM and high speed serial links will provide our infrastructure partners the lead they need to create next-generation networks.”
Technical Features of Cu-32 Design Kit
IBM’s High Speed Serial (HSS) cores were developed to provide industry-leading jitter performance and equalization support for enhanced system performance with the lowest possible bit error ratio. IBM is an active member of the Optical Internetworking Forum committee and is leading the effort to define interface standards for networking communication applications.
- Cu-32 offers the industry’s first set of HSS cores in 32nm SOI technology including:
- 15G Backplane core supporting 16G Fibre Channel standard
- 15G Chip-to-Chip core supporting low-power optical and chip-to-chip applications
- 28G Backplane core supporting 32G Fibre Channel standard
- 6G standards core supporting PCI-Express Gen1 & Gen2 standards
- PCI-Express Gen3 core supporting PCI-Express Gen1, Gen2, and Gen3 standards
IBM, as the first provider of eDRAM technology in a custom-logic design system continues to expand its eDRAM offering with a compiler that can create more than 3,000 configurations. This flexibility enables smarter silicon solutions with memory optimized for a wide range of applications from high-end servers and networking applications to game processors.
- IBM’s eDRAM offering features the fastest and densest eDRAM memory in the industry, achieving up to 600 MHz of random cycle performance while using up to ten times less standby power than conventional SRAM.
- IBM’s trench-based eDRAM technology is optimized to deliver high performance and low power, while avoiding many of the process complexities of alternative MIM-cap-based eDRAM cells.
IBM’s high-k metal gate (HKMG) SOI technology can provide up to 25% chip performance improvement, up to 30% improved energy efficiency with up to twice the density compared to 45 nm SOI technology, allowing chips built with the Cu-32 process to address an ever wider range of devices and applications.
Design kits for standard cell libraries, memory compilers, eDRAM and supporting Fibre Channel HSS standards are available now with additional HSS standards availabilities slated for end of 2010. IBM’s accreditation as a Trusted Supplier enables government sponsored program access to Cu-32 offering.
For further information about Cu-32 and IBM Microelectronics Division, visit https://www.ibm.com/chips/
(1) Cell phone uses a control channel for call setup. The control channel also provides the pathway for SMS messages. The message flows through the SMSC, then to the tower.
* 740 Billion text messages (1H09) or 1.5 Trillion messages full-year 2009 (Source: CTIA Wireless Association)
* 6.1 Trillion text messages WW in 2010 (Source: ITU)
* Max text message size: 140 Bytes
* Total # of Bytes transferred
– 1.5 Trillion * 140 Bytes = 210 TB = 1600 TeraBits = 1.6 PetaBits
– 6.1 Trillion * 140 Bytes = 854 TB = 6832 TeraBits = 6.8 PetaBits
* WW deployment of BTS: ~5 Million
* WW BTS Downlink capacity: 5 Million * 1 Gbps = 5 Peta-bps
* WW BTS Uplink capacity: 5 Million * 0.5 Gbps = 2.5 Peta-bps
* WW Backhaul network capacity: 5 Million * 1 Gbps = 5 Peta-bps
* End-to-End message transfer time
– Uplink + Backhaul + Dnlink
– 6.8Pb/2.5Pbps + 6.8Pb/5Pbps + 6.8Pb/5Pbps = 2.7 + 1.4 + 1.4 = 5.5 (<10 sec)
(2) (3) Every motion picture ever produced to be streamed in less than one minute.
-> WW movie production per year: 4,000
-> Total movies produced in 100 years: 400K (Upper bound 1M movies)
-> 4.4 GB per DVD * 1M movies = 36PetaBits
-> Time to stream = 36 PetaBits/ 1Pbps = 36 sec = <1 min
* 4G/LTE-Advance Downlink rate: 1.0 Gbps; MIMO; Single sector
* 4G/LTE-Advance Uplink rate: 500 Mbps; MIMO; Single sector
* 4G/LTE Advance Backhaul rate: 1.0 Gbps
* H.264 (MPEG-4 Part 10) movie
– 2 Hr SD Movie: 1 GB
* Time to download SD movie: 1 GB * 8 bits / 1Gbps = 8 sec (< 10 sec)
– 2 Hr HD Movie: 6 GB
* Time to download HD movie: 6 GB * 8 bits / 1 Gbps = 48 sec (< 1 min)
* H.264 Encoder Data rate: 6-12 Mbps
* 2 Hour HD movie = 2 Hr * 60 Mins/Hr * 60 Sec/Min * 6 Mbps = 5.4 GB
(4) ITU: “The World in 2010”