Tag Archives: hardware architecture

Transactional Memory: An Idea Ahead of Its Time

Nearly 20 years ago, two Brown University computer scientists were working on a largely theoretical problem: How could multiple parallel processors make changes to shared resources safely and efficiently? Their proposal — transactional memory — is sparking fresh interest as a new generation of processors seeks improved power and speed.

In 1993, Maurice Herlihy and a colleague published a paper on transactional memory — a new, clever tactic in computing to deal with handling shared revisions to information seamlessly and concurrently. Few noticed.

Nearly 20 years later, transactional memory is an idea that’s now the rage in hardware computing, and Herlihy, computer science professor at Brown University, has morphed into a prophet of sorts, a computing pioneer who was far ahead of his time. Intel recently announced that transactional memory will be included in its mainstream “Haswell” hardware architecture by next year. IBM has adopted transactional memory in the Blue Gene/Q supercomputer. The original paper by Herlihy and Eliot Moss has been cited more than 1,300 times. (more…)

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